NXP Semiconductors /MIMXRT1011 /IOMUXC /SW_MUX_CTL_PAD_GPIO_SD_10

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Interpret as SW_MUX_CTL_PAD_GPIO_SD_10

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: FLEXSPI_A_SCLK of instance: FLEXSPI

1 (ALT1): Select mux mode: ALT1 mux port: LPSPI2_SDO of instance: LPSPI2

2 (ALT2): Select mux mode: ALT2 mux port: LPUART2_TXD of instance: LPUART2

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO1_IO16 of instance: FLEXIO1

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: GPIO2

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_SD_10

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